Booster voltage generators are provided with integrated circuit memory devices to reduce the loss of data having a high logic level during active restoring operations by dropping a threshold voltage of the NMOS isolation gate. The loss of data having a high logic level may occur when multiple memory cells share a sense amplifier including a P-type sense amplifier (PSA) and an N-type sense amplifier (NSA) between isolation gates to reduce the size of the memory device. Moreover, as memory devices become more highly integrated, the load on a word line operating during a memory cycle may increase thus increasing the time required to enable the word line and decreasing the operating speed. In response, internal booster voltage generators have been provided on memory devices to reduce these problems. In particular, internal booster voltage generators may include a main pump to operate during stand-by conditions and an active kicker to operate when activated.
A dynamic random access memory (DRAM) generally operates using an optional refresh cycle wherein a dissipated charge varies according to the number of cells operating during a cycle. If the dissipated charge is greater than the supply charge, a memory malfunction may occur. Furthermore, if the supplied charge is greater than the dissipated charge, the reliability of the memory device may decrease as a result of the excessive charge.
A conventional method for controlling an internal booster power source of an integrated circuit memory device will now be discussed with reference to FIG. 1. This memory device includes a booster power line 13, a standby booster voltage generator 23, and a plurality of booster voltage active kickers 15, 17, 19, and 21. The standby booster voltage generator 23 is connected to the booster power line 13 and supplies a booster voltage Vpp to the memory device during standby operations. In this device, one-quarter of the memory cells are activated during a 4K refresh cycle as compared to the number of memory cells activated during a 1K refresh cycle. Accordingly, less power is dissipated during the 4K refresh cycle. By activating a reduced number of the memory cells, the memory device can operate using a reduced number of booster voltage active kickers.
If a sufficient number of booster voltage active kickers are provided so that any refresh cycle can be accommodated and if the refresh cycle is large, when fewer than all of the memory cells are activated excessive charge may cause an excessive voltage rise on the booster voltage power line thereby causing oxide breakdown, junction breakdown, or deterioration of the transistors. Referring now to FIG. 2, when the row address strobe signal RASB is enabled to the logic low level, the control signal PR rises to the logic high level to start the operation cycle.